Flash EEPROMs are characterized by the fact that all the memory cells of the memory array, or at least large groups of them (memory sectors), can be electrically erased at a time.
According to a preferred erasing technique, described for example in the co-pending European Patent Application No. 95830253.1 filed on Jun. 19, 1995 in the name of the same applicant, erasing of the memory cells of the memory array or of a given memory sector is performed by biasing the word lines of the memory array or of the memory sector with a negative erase voltage ranging from -8 V to -12 V, and applying a positive erase voltage of approximately 5 V to the sources of the memory cells. Applicant also incorporates by reference European Patent Application No. 95830348.9, filed Jul. 31, 1995 (corresponding to U.S. Pat. No. 5,719,807) European Patent Application No.95830317.4, filed Jul. 24, 1995 (corresponding to U.S. application Ser. No. 08/687,145) and European Patent Application No.95830351.3, filed Aug. 2, 1995 (corresponding to U.S. application Ser. No. 08/692,936).
After the erase, all the word lines and all the sources of the memory cells of the memory array or of the memory sector must be brought to the ground potential. This involves the discharge of large capacitances. In fact, when the potential of the word lines is brought to the negative erase voltage, the control gate capacitances of all the memory cells connected to the word lines are charged to a voltage ranging from -8 V to -12 V. Similarly, when the potential of the sources of the memory cells is brought to the positive erase voltage, the source capacitance of all the memory cells is charged to a voltage of approximately 5 V. In Flash EEPROM of the size of some megabits, the sum of the control gate capacitances, as well as the sum of all the source capacitances of the memory cells, can be of the order of some hundreds of picofarads. The rapid discharge of such large capacitances gives rise to high currents flowing in the metal lines which deliver the power supply voltages inside the memory device. To prevent problems of electromigration in such metal lines, these must be overdimensioned, with an obvious increase of chip area.